1. Field of the Invention
The invention relates to a film or layer of semi-conducting material and to a process for producing the film or layer.
2. Description of the Related Art
What are known as SOI (silicon on insulator) wafers have a layer structure generally comprising a carrier, for example a silicon wafer, a layer of oxide which is buried just below the surface and a thin layer of silicon on top of the layer of oxide. For the fabrication of electronic components (e.g. memories and microprocessors), this layer structure has significant advantages over the silicon wafers which are customarily used:
A better characteristic of the electronic functions is achieved, in combination with high switching speeds and a lower power consumption on the part of the component. Moreover, components which are fabricated on the basis of SOI wafers are more suitable for operation at relatively low voltages than conventional components.
For these reasons, in future generations of components, the use of SOI wafers will increase significantly. The quality demands imposed on the SOI wafers are high, in particular with regard to the layer thickness homogeneity and the defect densities in the thin layer of silicon and in the oxide layer. In this context, the various production processes and products in accordance with the prior art also differ:
For example, in the case of what is known as the SIMOX process, a layer with a high oxygen content is produced by implantation of oxygen ions through the surface of a silicon wafer over a defined depth which is determined by the energy of the oxygen ions (Izumi et al., Electron Lett. 14 (18) (1978), p. 593). In a subsequent heat treatment, this layer is converted into a layer of silicon oxide which separates the thin layer of silicon above it from the remainder of the silicon wafer, which lies below it. However, the implantation of the oxygen ions produces crystal defects (damage) in the thin layer of silicon, and this damage has adverse effects on the SOI wafer during subsequent fabrication of electronic components.
Generally, however, SOI wafers are produced by transferring a thin layer of silicon from a first wafer, the substrate wafer, to a second wafer, the carrier wafer. Generally, both wafers consist of silicon. The thin layer of silicon is joined to the carrier wafer for example via an insulating silicon oxide layer. A number of processes which can be used to transfer thin layers of silicon from a first wafer to a second wafer and therefore produce an SOI wafer are known:
In what is known as the SMARTCut process (U.S. Pat. No. 5,374,564; Weldon et al., J. Vac. Sci. Technolo., B 15 (4) (1997), pp. 1065-1073), the separating layer is produced by means of hydrogen implantation, and after the bonding of the two wafers the separation (splitting) is carried out by means of a heat treatment. The result is a relatively rough surface with a large number of defects, which then has to be smoothed by polishing or heat treatment (annealing). In the process, irreparable defects (holes), known as HF defects, are also formed in the thin, upper layer of silicon, with a density of 0.1/cm2-0.5/cm2. Furthermore, the implantation, the separating layer used and the separating process give rise to the formation of defects in the upper layer of silicon, which become visible after a Secco etching step (Secco etch defects) of an order of magnitude of 1·102/cm2 to approximately 1·104/cm2 (J. G. Park, “Nature of Surface Defects in SOI wafers: SIMOX vs. Bonded SOI”, JSPS, 3. International Symposium on Advanced Science and Technology of Silicon Material, 2000, Kona, USA).
In what is known as the ELTRAN process (U.S. Pat. No. 5,854,123; Yonehara et al., Electrochem. Soc. Proc. 99-3 (1999) pp. 111-116), the separating layer is produced by means of an anodic etching process, with a porous surface layer being formed. This layer forms the separating layer. Then, an epitaxial layer, which forms the subsequent thin layer of silicon, is deposited on this porous layer. The separation is carried out thermally or mechanically, with defects once again being formed in the surface and in the upper layer of silicon. Furthermore, the epitaxial layer cannot grow on the porous surface without any defects at all. The HF defect density (holes in the thin layer of silicon) is 0.1/cm2-0.3/cm2, the density of Secco etch defects is 5·102/cm2-1·105/cm2, depending on the layer thickness of the silicon layer. The surface roughness after splitting is high, at 5 nm rms (scanning area 1 μm×1 μm) and requires subsequent smoothing processes (Sakaguchi et al., Solid State Technology 43 (6)·(2000) pp. 88-92).
A further process is known as the Nano-cleave process developed by SiGen, USA (Current et al., European Semiconductor, 22(2) (2000) pp. 25-27). This process requires an additional smoothing step after the separation in order to produce roughness values of below 0.2 nm rms (Thilderkvist et al., IEEE SOI Symposium, 2000, Wakefield, USA).